1. Field of the Invention
The present invention relates to a method for forming an ultra-shallow junction in a semiconductor substrate, and more particularly, to a method for forming an ultra-shallow junction in a semiconductor substrate using a nuclear stopping layer.
2. Description of the Prior Art
Shallow junction or ultra-shallow junction formation might be one of the most important issues in MOSFET scaling. As known in the art, in order to suppress short channel effect, the junction depth of source and drain (S/D) extensions should be reduced as gate length becomes shorter. According to the prediction of SIA roadmap for ULSI technology, the S/D junction depth for 1.8 micron technology is between 40 nm˜60 nm, and is between 20 nm˜40 nm for 0.12 micron technology. However, as device sizes are scaled down more rigorously, the conventional methods for the fabrication such as ion implantation and rapid thermal annealing show the limits in satisfying the requirements of the SIA roadmap.
Various antimony (Sb) implantation methods have been investigated and have been applied to the fabrication of sub 0.1-micron gate MOSFET devices having ultra-shallow junction depths, since antimony (Sb) ions are heavier and less diffusive than arsenic (As) ions. U.S. Pat. No. 6,191,012 filed Feb. 20, 2001 by Ng, et al., entitled “Method for forming a shallow junction in a semiconductor device using antimony dimer”, teaches an antimony dimer implantation process including steps of ion implanting a molecular antimony dimer (Sb2+) into a semiconductor substrate. The antimony dimer implantation process creates a shallow doped junction having a high dopant concentration and a shallow junction depth. The antimony dimer ion is extracted from an antimony source material at an extremely low extraction voltage. A shallow doped region having a dopant concentration of about 1.0E17 to at least the solid solubility of antimony in silicon (1.0E20 atoms/cm3) is obtained with a junction depth ranging from about 5 to 80 nanometers.
U.S. Pat. No. 6,329,704 filed Dec. 11, 2001 by Akatsu, et al., entitled “Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer”, and U.S. Pat. No. 6,387,782 filed May 14, 2002, which is a division application of U.S. Pat. No. 6,329,704, teach a process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate.